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DDR Signal Integrity Simulations – Eyes Wide Open

Verify your memory bus performance with virtual compliance simulation (JEDEC)

PCBs have become so dense that it is easier to simulate the impact of PCBs on bus performance than to measure it. Virtual compliance simulation for DDR3/4 buses takes into account the full impact of the PCB on memory bus performance. Additionally, the simulation allows the bus lines to be implemented inside the board reducing cross-talk. What could be more convenient than knowing that a critical bus will perform to specifications before the first prototype is ordered?

Do you know the memory bus performance of your product?

The processors and memory buses on current electronics boards have become extremely fast requiring an understanding of high-speed signal behavior on printed circuit boards (PCB).Therefore, it has become very important to keep one’s ‘eyes open’. Figure 1 illustrates how memory lane signal is distorted with only the impact of a memory connector [1].

DD4 bus eye diagrams

Figure 1. DDR4 bus eye diagrams [1]

How experts do it

Experts from Etteplan, Janne Ahonen and Janne Pelander, have both taken a simulation approach in order to understand what is happening in the memory buses. Nowadays, it is crucial to simulate the memory bus. Often, they perform a post-analysis on inoperable memory buses by identifying and correcting the weaknesses of the lines on the PCB. In a more preferable situation, they perform the simulation on the bus before the PCB design is finalized. This approach may significantly reduce the number of required prototypes and shorten the time to market for the product.

Their approach to simulation is relatively straightforward. If possible, first simulate the memory directly connected to the central processing unit (CPU). This simulation provides ideal conditions for the signals. Then connect a simple PCB bus model between the CPU and the DDR3 memory and, by varying the length of the bus and values of the terminating resistors, identify the performance degradations. Finally, the simulation of the real PCB model with full stack up, via holes and connectors, will tell the whole story of the performance. Additionally, if the chip and component process windows are known, a simulation where the impact of variations is analyzed is possible as well.

Benefits of signal integrity simulations

Knowledge of the DDR bus performance before ordering the prototype can lead to less prototyping rounds which can significantly shorten the time to market for the product as well as potentially lower total R&D costs. Moreover, the quality of the product can be increased by reducing cross talk on the board, and the products power consumption reduced since a lower bus current drive is required. Essentially, a better and a more efficient product can be the end-result.

Verify your memory bus performance with Etteplan

Etteplan offers a one stop shop for testing and simulation needs. Etteplan has the expertise and understanding on high speed signal behavior on PCBs and the capabilities to perform signal integrity simulations on your product. We rely on our years of experience in using signal integrity simulations in projects as a common tool. Hence, we don’t only test your product but also provide problem solving and guide you in enhancing the performance of your product. Learn more!

Jani Vauto

Jani Vauto

Director, Wireless Solutions
+358 46 851 5965
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